module PC(
        input  clk,
        input  rst,
        input  [31:0] nextPC,
        output [31:0] currentPC
    );
    reg [31:0] PC;
    always @(posedge clk) begin
        if(rst)
            PC<=32'h00003000;
        else
            PC<=nextPC;
    end
    assign currentPC=PC;
endmodule
